The present invention relates generally to analog-to-digital converters, and specifically to analog-to-digital converters having folded differential logic encoding architectures.
As speeds of operation of electronic equipment increase, analog-to-digital converters (ADCs) need to operate at increasing rates in order not become a bottleneck in the operation of the equipment. A known architecture in the electronic art, which inherently comprises a fast system for analog-to-digital conversion, is xe2x80x9cflashxe2x80x9d architecture, wherein a number of comparators operate simultaneously and in parallel. The readout of a flash ADC is substantially a xe2x80x9cone-stepxe2x80x9d process.
FIG. 1 is a schematic block diagram of an m-bit flash analog-to-digital converter (ADC) 10, as is known in the art. Flash ADC 10 comprises a series resistor ladder 12, having 2m equal valued resistors coupled to a first reference voltage Vr1 and a second reference voltage Vr2, which generate 2m sequential potentials. The potentials are respectively applied to a first input of 2m comparators 14, which have a voltage Vin to be digitized applied to a second input of the comparators. The output of the comparators is in the form of thermometer code, which is converted to binary code by a decoder 16. Decoder 16 typically uses conversion from thermometer code to Gray code as an intermediate step, in order to reduce the effects of sparkles and meta-stability in the thermometer code. ADC 10 is typically implemented as a very large scale integrated circuit (VLSI).
ADCs of the form of ADC 10 have the advantage of one-step digitization, but typically suffer from disadvantages including large input capacitance to the comparators, especially as the number of bits, m, of the ADC increases. Furthermore, as speeds of operation of ADCs increase, the effects of the input capacitance are exacerbated. A number of methods are known in the art for improving the performance of ADCs such as ADC 10, two of these methods being described hereinbelow. A first method is to use a folding architecture after the comparators.
FIG. 2 is a schematic electronic diagram of a 3-bit ADC 20 using a folding architecture analog-to-digital encoder (ADE), and giving a Gray code output, as is known in the art. Differential outputs from differential preamplifiers 22A, 22B, . . . , 22G are input to respective differential pairs of transistors 24A, 24B, 24G. Each differential pair of transistors is driven by a current source delivering a current I0. A preamplifier and its coupled differential transistor pair acts substantially as a comparator. As shown in the diagram, the outputs of groups of the differential pairs are added, and the summed outputs generate respective potentials across resistors 25A, 25B, . . . , 25F. The outputs of the differential pairs are connected to comparators 26, 28, and 30, so as to generate Gray code outputs D0, D1, and D2 respectively. Comparator 26, generating the least significant bit (LSB), receives its potential inputs from current source 32 and differential pairs 24A, 24C, 24E, and 24G feeding through resistors 25E and 25F. Since four differential pairs are summed, comparator 26 has a folding factor of 4. Comparator 28 receives its potential inputs from current source 34 and differential pairs 24B and 24F feeding through resistors 25C and 25D. Since two differential pairs are summed, comparator 28 has a folding factor of 2.
The Gray code output for a folded differential logic (FDL) ADE of the form of FIG. 2 is described by the following general equation:                               G          i                =                                                            ∑                                  k                  =                  0                                                  k                  =                                                            2                                              n                        -                                                  (                                                      i                            +                            1                                                    )                                                                                      -                    1                                                              ⁢                              xe2x80x83                            ⁢                                                                    (                                          1                      +                                                                        (                                                      -                            1                                                    )                                                k                                                              )                                    2                                ⊕                                  T                                                            k2                                              i                        +                        1                                                              +                                          2                      i                                                                                            +            Bias                     greater than                                     ∑                              k                =                0                                            k                =                                                      2                                          n                      -                                              (                                                  i                          +                          1                                                )                                                                              -                  1                                                      ⁢                          xe2x80x83                        ⁢                                                            (                                      1                    +                                                                  (                                                  -                          1                                                )                                                                    k                        +                        1                                                                              )                                2                            ⊕                              T                                                      k2                                          i                      +                      1                                                        +                                      2                    i                                                                                                          (        1        )            
wherein Tj is the jth bit of the thermometer code, and Bias=1 for all j except the most significant bit, when Bias=0. In equation (1) the two expressions on either side of the inequality are evaluated first, and Gi is set according to which side of the inequality is larger. The xe2x80x9cBiasxe2x80x9d term is needed in order that the encoder corresponding to the equation functions correctly.
Applying equation (1) to ADC 20, wherein n=3, gives:
G0=T1+{overscore (T)}3+T5+{overscore (T)}7+1 greater than {overscore (T)}1+T3+{overscore (T)}5+T7;
G1=T2+{overscore (T)}6+1 greater than {overscore (T)}2+T6; andxe2x80x83xe2x80x83(2)
G2=T4 greater than {overscore (T)}4
FIG. 3 is a schematic electronic diagram of an ADE section 40 of a 5-bit ADC giving a Gray code output, as is known in the art. Section 40 is implemented in a generally similar manner to those elements of ADC 20 which generate the LSB. ADE section 40 has a folding architecture comprising 16 comparators 42, each generally similar to the comparators described with reference to FIG. 2 formed by coupling a differential preamplifier to a differential transistor pair. (Only odd-numbered comparators are shown since these are the only comparators involved in generating the LSB.) Outputs from comparators 42 feed one comparator 44. Equation (1) for output G0 of comparator 44, wherein n=5, becomes:
G0=T1+{overscore (T)}3+. . . +T29+{overscore (T)}31+1 greater than {overscore (T)}1+T3+. . . +{overscore (T)}29+T31xe2x80x83xe2x80x83(3)
FIG. 4 illustrates a section 50 of a flash ADC, as is known in the art. Comparators 54 and 56 are coupled at their inputs to resistors 58 and 60 comprised in an input series resistor ladder. Outputs of comparators 54 and 56 are coupled to series resistor chains 51 and 53. While comparators 54 and 56 are theoretically step-function elements generating either a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d depending on the difference at their input, in practice each comparator acts as an amplifier having an output between 1 and 0. The outputs of resistor chains 51 and 53 similarly vary in a generally linear manner between 0 and 1. The outputs from resistor chains 51 and 53 act as interpolated outputs of comparators 54 and 56, and these outputs are applied to comparators 55. The outputs of comparators 55, which may be the final outputs of the ADC or which may processed further, thus effectively interpolate between the outputs of comparators 14, so increasing the resolution of the ADC. The circuit of FIG. 4 shows an interpolation depth of 4. Combinations of folding architectures, as described with reference to FIGS. 2 and 3, and interpolation techniques, as described with reference to FIG. 4, are known in the art.
U.S. Pat. No. 6,014,098, to Bult et al., whose disclosure is incorporated herein by reference, describes an ADC using a preamplifier before each initial comparator. Outputs of the comparators are fed through cascaded stages of averaging amplifiers. The stages comprise folding, so that the cascading effectively implements multiple folding.
An article titled xe2x80x9cA 10-b 300 MHz Interpolated-Parallel A/D Converter,xe2x80x9d by Kimura et al., in IEEE Journal of Solid-State Circuits 28 (1993), which is incorporated herein by reference, describes an ADC using folded differential logic circuitry after interpolation resistors.
An article titled xe2x80x9cA 10-b 50 MS/s 500 mW A/D Converter Using a Differential-Voltage Subconverter,xe2x80x9d by Miki et al., in IEEE Journal of Solid-State Circuits 29 (1994), which is incorporated herein by reference, a describes an ADC using a differential two-step architecture. An input voltage is coarsely digitized in a first step to generate higher significant bits. In a second step the coarse digital signal is converted to an analog value, using a digital-analog converter, and this is subtracted from the initial input voltage. The result of the subtraction is further digitized to provide the lower significant bits. The article also describes how folding the input series ladder facilitates differential operation.
An article titled xe2x80x9cError Suppressing Encode Logic of FCDL in a 6-b Flash A/D Converter,xe2x80x9d by Ono et al., in IEEE Journal of Solid-State Circuits 32 (1997) , which is incorporated herein by reference, uses cascode circuitry at the output of initial comparators. The initial comparators are arranged in an FDL circuit, and the output of the comparators are input to the emitters of a pair of transistors in a cascode arrangement. The collectors of the transistors are input to a comparator, which, because of the intermediate cascoded transistors, is not affected by capacitance on the initial comparator output lines.
While the folding architecture exemplified by the circuits of FIG. 2 and FIG. 3 is a relatively simple system which is inherently fast, capacitance effects, especially for ADCs having larger numbers of bits, are still significant. The capacitance effects are more pronounced on long input lines such as the input lines to comparator 44 (FIG. 3). As rates of sampling for ADCs increase, the importance of minimizing line capacitance increases, since the capacitance effects increase time constants of the circuit. Furthermore, long folded architectures require correspondingly large bandwidths because of the increased number of xe2x80x9cfoldsxe2x80x9d in the signal.
In preferred embodiments of the present invention, a flash analog-to-digital converter (ADC) comprises a series resistor ladder. A reference voltage is applied to the ladder so as to generate sequential potentials, which together with an input analog voltage are fed to a plurality of folded differential logic (FDL) analog-to-digital encoders (ADEs). Each FDL-ADE is coupled to a respective section of the ladder, and generates a respective output responsive to the analog voltage input to the converter. The plurality of outputs of the FDL-ADEs are used as inputs to a resultant FDL encoder, which in turn generates a digital output corresponding to the input analog voltage.
The pyramidal structure of the present ADC, wherein the outputs of the first plurality of FDL-ADEs are coupled to the resultant FDL encoder, leads to lines of the total system within the ADC being substantially shorter than lines of an equivalent non-pyramidal ADC. Thus line capacitances are correspondingly reduced, and the bandwidth of the ADC is effectively increased. Also, by effectively breaking up one FDL-ADE into a plurality of shorter FDL-ADEs, bandwidth demands are reduced.
Each of the plurality of FDL-ADEs generates a respective binary partial sum of a specific bit. The bit, for example a least significant bit (LSB), corresponds to one of the bits of a digitized value of an analog input. The partial sums are in turn effectively summed by the resultant FDL encoder to generate a final binary output of the specific bit corresponding to the analog input. Preferably, all bits of the ADC are generated by a substantially similar process, so that each bit is formed by a plurality of FDL-ADEs generating partial sums which are effectively summed by a respective resultant FDL encoder.
In some preferred embodiments of the present invention, the ADC comprises three or more levels of encoders in a pyramid arrangement. A lowest level of ADEs generates first partial sums, which are summed in a smaller next level of encoders to form a second (smaller) plurality of partial sums. The second plurality of partial sums are also summed, and the process of summing reducing numbers of partial sums continues until one value, corresponding to the final binary output, is generated.
There is therefore provided, according to a preferred embodiment of the present invention, an analog-to-digital converter (ADC), including:
a plurality of first-level folded-differential-logic-encoders (FDLEs), coupled to receive an analog input signal and respective reference voltages and to provide respective outputs responsive to comparing a magnitude of the input signal to the respective reference voltages; and
a second-level resultant FDLE, which is coupled to receive and combine the outputs of the first-level FDLEs to provide a digital value indicative of the magnitude of the input signal.
Preferably, each of the first-level FDLEs includes one or more differential preamplifiers coupled to respective transistor differential pairs, and each of the transistor differential pairs includes a respective current source driving the pair.
Preferably, each of the first-level FDLEs includes a comparator, and the outputs of the first-level FDLEs include differential outputs generated by the comparator responsive to inputs from the transistor differential pairs.
Further preferably, an input of the comparator is coupled to a bias current source, wherein the current source supplies a current having a value responsive to a constant term in a predetermined inequality defining an output of the comparator.
Preferably, the second-level resultant FDLE includes:
one or more transistor differential pairs, each pair including a respective current source driving the pair and generating an intermediate output; and
a comparator, which receives the intermediate outputs from the one or more transistor differential pairs and outputs the digital value responsive thereto.
Further preferably, an input of the comparator is coupled to a bias current source, wherein the current source supplies a current having a value responsive to a constant term in a predetermined inequality defining the digital value.
Preferably, the digital value includes one or more pairs of differential values.
Preferably, at least a part of the ADC is implemented using a bipolar technology.
Alternatively or additionally, at least a part of the ADC is implemented using a complementary metal oxide semiconductor (CMOS) technology.
There is further provided, according to a preferred embodiment of the present invention, an analog-to-digital converter (ADC), including:
a first plurality of first-level folded-differential-logic-encoders (FDLEs), coupled to receive an analog input signal and respective reference voltages and to provide respective first outputs responsive to comparing a magnitude of the input signal to the respective reference voltages; and
a second plurality of second-level FDLEs, which are coupled to receive and combine the outputs of the first-level FDLEs to provide a second plurality of intermediate outputs indicative of the magnitude of the input signal, wherein the second plurality is smaller than the first plurality; and
a third-level resultant FDLE, which is coupled to receive and combine the second plurality of intermediate outputs to provide a digital value indicative of the magnitude of the input signal.
There is further provided, according to a preferred embodiment of the present invention, a method for determining a digital value of an analog signal, including:
encoding the analog signal in a plurality of first-level folded-differential-logic-encoders (FDLEs) coupled to receive respective reference voltages, so as to provide respective outputs responsive to comparing a magnitude of the analog signal to the respective reference voltages;
receiving the outputs of the first-level FDLEs in a second-level resultant FDLE; and
generating in the second-level resultant FDLE the digital value responsive to the outputs of the first-level FDLEs.
Preferably, each of the first-level FDLEs includes one or more differential preamplifiers coupled to respective transistor differential pairs, and encoding the analog signal includes driving each of the transistor differential pairs with a respective current source.
Preferably, each of the first-level FDLEs includes a comparator, and encoding the analog signal includes generating differential outputs from the comparator responsive to inputs from the transistor differential
Preferably, the method includes:
coupling an input of the comparator to a bias current source; and
supplying a current having a value responsive to a constant term in a predetermined inequality defining an output of the comparator from the current source.
Preferably, the second-level resultant FDLE includes a comparator and one or more transistor differential pairs, each pair including a respective current source, and generating in the second-level resultant FDLE includes:
driving each of the pairs by its respective current source;
is generating an intermediate output from each of the pairs;
receiving the intermediate output from each of the pairs in the comparator; and
outputting the digital value responsive to the received intermediate output.
Further preferably, generating in the second-level resultant FDLE includes:
coupling an input of the comparator to a bias current source; and
supplying a current from the current source, the current having a value responsive to a constant term in a predetermined inequality defining the digital value.
Preferably, the digital value includes one or more pairs of differential values.
There is further provided, according to a preferred embodiment of the present invention, a method for determining a digital value of an analog signal, including:
encoding the analog signal in a first plurality of first-level folded-differential-logic-encoders (FDLEs) coupled to receive respective reference voltages, so as to provide respective first outputs responsive to comparing a magnitude of the analog signal to the respective reference voltages;
receiving the first outputs of the first-level FDLEs in a second plurality of second-level FDLEs, wherein the second plurality is smaller than the first plurality;
generating in the second-level FDLEs a second plurality of intermediate outputs indicative of the magnitude of the analog signal;
receiving the intermediate outputs of the second-level FDLEs in a third-level resultant FDLE; and
generating in the third-level resultant FDLE the digital value responsive to the intermediate outputs of the second-level FDLEs.
There is further provided, according to a preferred embodiment of the present invention, an analog-to-digital converter (ADC), including:
a first plurality of differential preamplifiers, coupled to receive an analog input signal and respective reference voltages and to provide respective first outputs responsive to comparing a magnitude of the input signal to the respective reference voltages;
a second plurality of interpolation resistor ladders, coupled to receive the respective first outputs and to provide respective interpolated outputs responsive thereto;
a second plurality of first-level folded-differential-logic-encoders (FDLEs), coupled to receive the respective interpolated outputs and to provide respective second outputs responsive to comparing magnitudes of the respective interpolated outputs; and
a second-level FDLE, which is coupled to receive and combine the second outputs of the first-level FDLEs to provide a digital value indicative of the magnitude of the input signal.
There is further provided, according to a preferred embodiment of the present invention, a method for determining a digital value of an analog signal, including:
inputting to a first plurality of differential preamplifiers the analog signal and respective reference voltages;
generating in the first plurality of differential preamplifiers a first plurality of first outputs responsive to the analog signal and the respective reference voltages;
interpolating the first outputs in a second plurality of interpolation resistor ladders coupled to the first plurality of differential preamplifiers so as to generate respective interpolated outputs responsive to the first outputs;
encoding the interpolated outputs in a second plurality of first-level folded-differential-logic-encoders (FDLEs) coupled to receive the respective interpolated outputs and to provide respective second outputs responsive to magnitudes of the interpolated outputs;
receiving the second outputs of the first-level FDLEs in a second-level resultant FDLE; and
generating in the second-level resultant FDLE the digital value responsive to the second outputs of the first-level FDLEs.
The present invention will be more fully understood from the following detailed description of the preferred embodiments thereof, taken together with the drawings, in which: